A display device for a portable electronic device such as a mobile telephone is required to consume little power and to exhibit a high image quality. Accordingly, it is desired that the driver circuit of the display device consume little power and be small in size.
The specification of Japanese Patent Kokai Publication No. JP-P2002-215108A (see FIG. 13 of the specification) discloses a circuit whereby a display device for a portable electronic device such as a mobile telephone is driven with little consumption of power.
FIG. 16 is a block diagram of a 6-bit (64-gray-level) data electrode driving circuit according to the prior art, and FIG. 17 is a detailed circuit diagram of the main components of a driver unit.
As shown in FIG. 16, the driving circuit includes a data buffer circuit 136, which retains, for a prescribed period of time, image signals (D00 to Dxx) input serially in sync with a clock signal CLK, for driving a data bus; a bidirectional shift register circuit 132 to which a horizontal start signal STH is input for generating a sampling signal that has been synchronized to the clock signal; a data register circuit 134 for expanding and holding a digital image signal that enters serially in accordance with the sampling signal that is output from the shift register circuit 132; a data latch circuit 170 for holding all digital image signals in unison in accordance with a latch signal STB; a decoder circuit 160 for decoding the image signals; a grayscale voltage generating circuit 180 for generating grayscale voltages having 64 values set beforehand so as to conform to the gamma characteristic of a liquid crystal; a grayscale selecting circuit 110 for selecting one value from the 64 grayscale voltages in accordance with the image signal; a voltage follower circuit 120 to which the voltage selected by the grayscale selecting circuit 110 is input for driving data electrodes at high speed; a changeover circuit 140 for switching between a connection between the voltage follower circuit 120 and data electrodes 150 and a connection between the grayscale selecting circuit 110 and the data electrodes 150; and a control circuit 138 for controlling the changeover circuit 140, etc.
In FIG. 16, the data register circuit 134, data latch circuit 170, decoder circuit 160, grayscale selecting circuit 110, voltage follower circuit 120 and changeover circuit 140 are individual circuits the number of each of which conforms to the number of data electrodes 150. For example, FIG. 17 represents in detail the main components of a driver unit in regard to a case where there are three data electrodes 150. As shown in FIG. 17, there are decoder circuits 16R, 16G, 16B, grayscale selecting circuits 11R, 11G, 11B and voltage follower circuits 121, 122, 123 provided in correspondence with electrodes 151, 152, 153, respectively. Further, there are switches 141, 142, 143 for connecting the outputs of respective ones of the grayscale selecting circuits 11R, 11G, 11B to electrodes 151, 152, 153, respectively, and switches 131, 132, 133 for connecting the outputs of respective ones of the voltage follower circuits 121, 122, 123, to which the outputs of the grayscale selecting circuits 11R, 11G, 11B, respectively, are input, to the electrodes 151, 152, 153, respectively. The switches 141, 142, 143, 131, 132, 133 correspond to the changeover circuit 140.
Each of the grayscale selecting circuits 11R, 11G, 11B is constituted by 64 analog switches SW0 to SW63 (transfer switches or the like using P-channel transistors and N-channel transistors) of the kind shown in FIG. 19. Grayscale voltages V0 to V63 are applied as inputs to respective ones of the switches, one value is selected from among the 64-value voltages of V0 to V63 and this value is input to the voltage follower circuit 120 and changeover circuit 140.
FIG. 20A illustrates an example of the individual circuits of the decoder circuit 160 and grayscale selecting circuit 110 when an image signal is composed of two bits (D2, D1). The decoder circuit 160 uses NAND gates and inverter circuits. In order to simplify the drawing, the illustrated example is such that the image signal is composed of the two bits and the grayscale selecting circuit 110 is shown as using N-channel transistors, with P-channel transistors being omitted. FIG. 20B illustrates which of the grayscale voltages V0 to V3 is selected and output by the logic of the two bits (D2, D1) in FIG. 20A.
Further, as illustrated in FIG. 21, the grayscale selecting circuit 110 is composed of two transistors, namely an enhancement-type transistor and a depletion-type transistor, and is capable of implementing a decoder function. In such case the decoder circuit 160 is unnecessary. If the arrangement of FIG. 20 is adopted, switch output impedance declines. If the arrangement of FIG. 21 is adopted, a disadvantage is that output impedance rises because a plurality of transistors are connected serially. An advantage, however, is that the area occupied by the device can be reduced because a decoder circuit is not required.
In FIG. 16, the grayscale voltage generating circuit 180 has a plurality of resistors connected in series and generates 64-value grayscale voltages of positive and negative polarities in dependence upon a polarity signal POL.
Further, the power-supply voltage of the drive system of grayscale selecting circuit 110 and voltage follower circuit 120, etc., is higher than that of the circuits (data register circuit 134, etc.) ahead of the data latch circuit 170 and therefore a level shifting circuit (not shown) is inserted on the input side or output side of the data latch circuit 170.
A high driving performance and a broad dynamic range are required as characteristics of the voltage follower circuit 120. There are many cases, therefore, in which a differential input stage is constituted by a rail-to-rail-type amplifier and an output stage as push-pull amplifier.
The operation of the changeover circuit 140 (switches 141, 142, 143, 131, 132, 133) will be described with reference to the timing chart of FIG. 18.
First, if the latch signal STB enters at the “H” level, the image signals held in the data register circuit 134 are transferred to and held in the data latch circuit 170 in unison and one value from among the 64 grayscale-voltages is selected by the grayscale selecting circuit 110 in accordance with the image signals. The changeover circuit 140 at this time is turned off so that no signals are connected to the electrodes 150.
Next, the latch signal STB is sent to the “L” level, the changeover circuit 140 is changed over by the control circuit 138 (the switches 131, 132, 133 are turned on) and the data electrodes 150 (151, 152, 153) are driven at high speed by the voltage follower circuit 120 (121, 122, 123). Next, when the changeover circuit 140 is changed over (switches 131, 132, 133 are turned off and switches 141, 142, 143 are turned on), the data electrodes 150 (151, 152, 153) are driven directly by the voltages selected by the grayscale selecting circuit 110. When driving of the scanned electrodes ends, the changeover circuit 140 is turned off (switches 141, 142, 143 are turned off). Over the interval during which drive is being performed by the grayscale selecting circuit 110, the bias current of the voltage follower circuit 120 (121, 122, 123) is interrupted and the voltage follower circuit 120 (121, 122, 123) is deactivated so that power consumption can be reduced. An AP signal is one that controls a constant-current source of the voltage follower circuit. This signal controls the bias current value in FIG. 17.
The specification of Japanese Patent Kokai Publication No. JP-A-8-129362 (see FIG. 2 of the specification) discloses an example in which a plurality of data electrodes are driven by a single grayscale voltage selecting circuit.
The specification of Japanese Patent Kokai Publication No. JP-A-11-327518 (see FIGS. 1 and 5 of the specification) discloses an apparatus, which is based upon dot-inversion drive, for driving 3′-number of electrodes by a time-division switch and inverting the polarity of an output signal in time-division fashion.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2002-215108A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-8-129362
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-A-11-327518